SOC Low Power Design Engineer
- Location: San Diego, California
Join the team of one of the leading semiconductor companies in the business.
This is a great way to get your foot in the door!
Located in the northern section of San Diego, CA, right off 85
$64 to $81
Do you have a passion for helping people and getting things done? Do you possess a unique blend of helpfulness, drive, and attention to detail that transforms ambiguous goals into a concrete results? If so, then we’d like to meet you!
- Familiar with low power design techniques and power structural verification.
- Experienced in using Cadence Conformal Low Power tool for structural power verification and PrimeTime Power Analysis Tool.
- Have a Bachelor's degree in Electrical or Computer Engineering.
- ASIC frontend development Logic design, RTL coding, verification, synthesis, and timing closure .
- Hardware description languages (Verilog, VHDL, System Verilog).
- Power-aware implementation flow, including UPF/CPF/Conformal Low Power.
- Check Power simulation/analysis tool (PtPx/PowerArtist)
The Global SoC Power team is responsible for low power implementation and power analysis at SoC level design. This includes defining low power requirements implementation of digital, mixed-signal circuits and systems that are integrated into System-on-Chip (SoC). Power analysis responsibilities includes SoC Baseline Power rollup, Core Power Requirements, Power Models for UC (use-case) power rollup at chipset level.
PREFERRED QUALIFICATION: Master's degree in Electrical or Computer Engineering Experience with/in: Experienced in low power design optimization techniques Familiarity of power islands, power gating, power sequencing and multi-voltage domain design Familiarity of overall SoC Infrastructure - Busses, CPUs, I/Os and DFT Components Scripting and coding with Perl/Tcl