Mask Designers - 14nm FinFET
- Location: San Jose, CA
The Layout Designer will be responsible for physical design of RF and Analog circuits in a fast paced environment. Minimum expectations include:
- Providing accurate schedules
- Meeting project milestone deadlines
- Full self-sufficiency in debugging complex verification failures
- Fully understanding the Cadence 6.1.6 and Calibre tools that we use.
- Delivering high quality layout that conforms to all design requirements.
- Full understanding of hierarchical planning (top down and bottom up) and integration
- Work on 28nm or 14nm FinFET circuits as team member in the Full Custom Layout environment.
- 5 to 10 years experience in RF/analog layout Design
- Custom layout experience must include high frequency circuits such as LNAs, Mixers, VCOs, etc.
- Full familiarity with Cadence Virtuoso and Mentor Graphics Calibre tools
- 40nm, 28nm and 14nm FinFET design processes
- Able to work in a team environment with other Mask Designers and Design Engineer's
- Needs to have 4 to 5 years of 28nm and 14nm FinFET experiences.
- Outstanding written and verbal communication
- 28nm and 14nm FinFET processes experience
- Proficiency with Cadence Virtuoso IC6.1.6 and IC12.2 (OpenAccess)
- Proficiency in the Full Custom RF Analog Layout Design environment
- Proficiency with Calibre verifications tools.
Required: Associate's or equivalent experience