Design Verification Engineer
- Location: San Diego, CA
Currently seeking a digital verification engineer for the mixed-signal ASICs that support our mobile platforms for next generation 5G RFIC/PMIC/Codec technologies. Successful candidates will be working on the following: Block/Subsystem/SoC level digital IP verification using constraint-random coverage methodologies at both RTL and Gate Level.
BSEE and minimum 5 years experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies. The skills involved includes SV/UVM/UVM_REG/Randomization/Coverage/SVA. Minimum 5 years experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.
MSEE Preferred candidate will have experience in the following:
- Extensive hand on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage (covergroups), assertions (SVA), simulations, regression, debug, bug reporting/tracking.
-Experience in debugging RTL & Gate level simulations
-Part of multiple tapeouts with high quality verification.
Required: Bachelor's, Electrical Engineering